Nowadays, Integrated Circuits (ICs) are increasingly scaled down, and feature sizes thereof are becoming smaller and smaller and thus are approaching the theoretical limit of photolithography systems. Therefore, there are typically serious distortions in an image formed on a wafer by a photolithography, that is, Optical Proximity Effects (OPEs) occur. As the photolithography technology is facing more strict requirements and challenges, there has been proposed the Double Patterning Technology (DPT) which is able to enhance photolithography resolutions. In the DPT, a circuit pattern with a high density is divided into two separate patterns with lower densities, which are then respectively printed onto a target wafer.
Hereinafter, the line-and-cut DPT for making the gates in a conventional semiconductor device manufacture process is described with reference to FIGS. 1-3.
FIG. 1 shows a part of a layout of devices formed on a wafer. As shown in FIG. 1, a pattern of lines 1001 which is corresponding to the gate pattern to be formed is printed on the wafer by a photo resist coating and then an exposure through a mask. Here, active regions 1002 on the wafer are also shown. The respective lines of the pattern 1001 are printed in parallel in a single direction and have the same or similar pitches and critical dimensions.
Next, as shown in FIG. 2, cuts 1003 are formed in the pattern of lines 1001 by a further exposure through a cut mask. Thus, in the pattern 1001, gate patterns corresponding to different devices are separated from one another.
Finally, an etching is carried out with the photo resist pattern 1001 having cuts 1003 formed therein to arrive at gate structures corresponding to this pattern.
In the above processes, a single exposure for forming gate patterns is divided into two: one for exposing the pattern of lines 1001, and the other for exposing the cuts 1003. As a result, it is possible to reduce the demand for photolithography and improve the line width control in the photolithography. Further, it is possible to eliminate many proximity effects and thus improve the Optical Proximity Correction (OPC). Furthermore, it is able to ensure a good channel quality and thus guarantee a high mobility for carries in the channels.
Besides, as shown in FIG. 3, after the formation of gates 2002 on wafer 2001 by etching in the processes described above, it is often desired to form sidewall spacers surrounding the gates. Since there are cuts 1003 in the gate patterns, as shown in FIG. 2, the sidewall spacer material will enter inside the cuts 1003. Thus, the sidewall spacers of respective gate patterns on two opposite ends of a cut 1003 may merge with each other, resulting in defects such as voids in the cut 1003.
As shown in FIG. 3, after the main bodies of devices are formed, a dielectric layer 2003 may also be deposited on the wafer to electrically isolate the respective devices from one another. Thus, the defects such as voids in the cuts 1003 as described above will also cause defects in the formed dielectric layer. Moreover, in order to make contacts to the gates and sources/drains, contact holes corresponding to the gates and sources/drains may be etched in the dielectric layer 2003, and conductive materials such as metals may be filled therein, so as to form contacts 2004.
In this case, all the contacts, including those on the sources/drains and those on the gates, are manufactured by etching the contact holes to their bottoms at one time and then filling the contact holes with conductive materials. This makes a strict demand for the etching of the contact holes. For example, since the etching depth on the gate is different from that on the source/drain, a short is likely to occur between the gate and the contact hole. Further, since the etching on the source/drain is deeper while the corresponding opening is relatively small (that is, the width to height ratio is small), various problems, such as under-etching, generating voids in the filled metals, and the like, are likely to occur. This restricts the selection of manufacture processes and causes greater parasitic resistances as well.
In view of the above, there is a need for a novel semiconductor device structure and a method for fabricating the same.